1. Field of the Invention
The present invention relates to semiconductor devices provided between semiconductor substrates and gate electrodes with multilayer films each including an insulating film having a charge trap function and sandwiched by upper and lower insulating films, and methods of manufacturing the same.
2. Description of the Related Art
Conventionally, as a nonvolatile memory which can hold its stored data even after the power is cut off, a semiconductor memory has been devised, which includes an impurity diffusion layer formed in a semiconductor substrate to serve as bit lines (buried bit lines), and word lines formed over the semiconductor substrate with a capacitive insulating film being interposed between them, so as to run perpendicularly to the bit lines. The structure can be simpler than a two-layer electrode structure such as an EEPROM and is expected to cope with further size reduction and micropatterning of elements.
In this type of semiconductor memories, the capacitive insulating film preferably has a multilayer structure made up from at least three layers, in which an insulating film having a charge trap function, such as a silicon nitride film, is sandwiched by upper and lower insulating films, such as silicon oxide films. As a typical example of the multilayer film known is a structure of silicon oxide film/silicon nitride film/silicon oxide film, i.e., a so-called ONO film, in which a silicon nitride film having a charge trap function is sandwiched by upper and lower silicon oxide films.
In this type of semiconductor memories, since the word lines cross the buried bit lines, which serve as sources and drains, with the multilayer film being interposed between them, sufficient electrical insulation must be ensured between the bit lines and the word lines. Conventional methods of manufacturing semiconductor memories having buried bit line structures will be described below from the above viewpoint.
(Prior Art 1)
In this prior art, an ONO film is entirely used as an electrical insulating film between bit and word lines.
More specifically, as shown in FIG. 14A, a silicon oxide film 111, a silicon nitride film 112, and a silicon oxide film 113 are sequentially stacked in this order in an active region on, e.g., a p-type silicon semiconductor substrate 101 to form an ONO film 102. After a resist pattern 103 is formed on the ONO film 102, n-type impurities such as arsenic are ion-implanted into a surface layer of the semiconductor substrate 101 using the resist pattern 103 as a mask under such conditions that the ions can pass through the ONO film 102.
The resist pattern 103 is then removed through an ashing process or the like, and the semiconductor substrate 101 is annealed, thereby forming buried bit lines 104 that serve also as sources and drains.
As shown in FIG. 14B, an electrode material is deposited onto the ONO film 102 and patterned to form word lines 105 that cross the buried bit lines 104 with the ONO film 102 being interposed between them. The word lines 105 serve also as gate electrodes.
After that, post-processes such as formation of an insulating interlayer, contact holes, and various electrical interconnection layers are executed, thereby completing a semiconductor memory.
(Prior Art 2)
In this prior art, only the lowermost silicon oxide film of an ONO film on bit lines is made thicker to ensure electrical insulation.
More specifically, as shown in FIG. 15A, an ONO film 102 is formed in an active region on, e.g., a p-type silicon semiconductor substrate 101. After a resist pattern 103 is formed on the ONO film 102, the upper silicon oxide film 113 and the silicon nitride film 112 of the ONO film 102 are patterned using the resist pattern 103 as a mask, thereby leaving only the lowermost silicon oxide film 111 as it is.
Impurities of n-type such as arsenic are then ion-implanted into a surface layer of the semiconductor substrate 101 using the resist pattern 103 as a mask under such conditions that the ions can pass through the lowermost silicon oxide film 111.
The resist pattern 103 is then removed, and the semiconductor substrate 101 is annealed in an oxidative atmosphere, thereby forming buried bit lines 104 that serve also as sources and drains. At this time, as shown in FIG. 15B, accelerated oxidation occurs at portions of the silicon oxide film 111 above the bit lines 104 through the annealing process due to the presence of arsenic ions in the semiconductor substrate 101. The silicon oxide film 111 thereby has a thickness of about 40 to 60 nm at those portions.
As shown in FIG. 15C, an electrode material is then deposited and patterned to form word lines 105 that cross the buried bit lines 104 with the silicon oxide film 111 being interposed between them. The word lines serve also as gate electrodes.
After that, post-processes such as formation of an insulating interlayer, contact holes, and various electrical interconnection layers are executed, thereby completing a semiconductor memory.
(Prior Art 3)
In this prior art, to ensure electrical insulation, bit lines are formed with a thick silicon oxide film provided thereon.
More specifically, as shown in FIG. 16A, a thin sacrificial oxide film 106 is formed in an active region on, e.g., a p-type silicon semiconductor substrate 101. After a resist pattern 103 is formed on the sacrificial oxide film 106, n-type impurities such as arsenic are ion-implanted into a surface layer of the semiconductor substrate 101 using the resist pattern 103 as a mask under such conditions that the ions can pass through the sacrificial oxide film 106.
As shown in FIG. 16B, the resist pattern 103 is then removed, and the semiconductor substrate 101 is annealed in an oxidative atmosphere, thereby forming buried bit lines 104 that serve also as sources and drains. At this time, accelerated oxidation occurs at portions of the sacrificial oxide film 106 above the bit lines 104 through the annealing process due to the presence of arsenic ions in the semiconductor substrate 101. The sacrificial oxide film 106 thereby has a thickness of about 40 to 60 nm at those portions.
As shown in FIG. 16C, after the portions of the sacrificial oxide film 106 on the channel region is removed, an ONO film 102 is formed on the active region. At this time, the thickness of the sacrificial oxide film 106 above the bit lines 104 increases to about 50 to 90 nm because of the influence of the annealing process in forming the ONO film 102.
As shown in FIG. 16D, an electrode material is then deposited and patterned to form word lines 105 that cross the buried bit lines 104 with the sacrificial oxide film 106 being interposed between them. The word lines serve also as gate electrodes.
After that, post-processes such as formation of an insulating interlayer, contact holes, and various electrical interconnection layers are executed, thereby completing a semiconductor memory.
By any of the above-described manufacturing methods, a semiconductor memory having a buried bit line structure, which can hold electrical insulation between the bit and word lines, may be manufactured. However, the above manufacturing methods have the following problems.
In the manufacturing method described in the prior art 1, since electrical insulation between the bit lines 104 and the word lines 105 are ensured only by the ONO film 102, the breakdown voltage of the ONO film 102 must be made high. In this manufacturing method, however, since arsenic ions are ion-implanted through the ONO film 102 to form the bit lines 104, the ONO film 102 may be inevitably damaged. In addition, since the uppermost silicon oxide film 113 of the ONO film 102 may be partially or fully etched off through a post-process, it is hard to ensure a sufficient breakdown voltage of the ONO film 102.
In the manufacturing method described in the prior art 2, in thickening the silicon oxide film 111 above the bit lines 104 by annealing, only the silicon oxide film 111 is present above the bit lines 104. For this reason, bird's beaks may be formed on both sides of each channel region due to the wraparound by oxygen. In addition, since the peripheral circuit region is normally formed simultaneously with formation of the memory cell region, the silicon oxide film 111 above the bit lines 104 may become thicker (about 100 to 150 nm) through several times of annealing processes in forming the gate insulating films of transistors in the peripheral circuit region, and accordingly, larger bird's beaks may form.
In the manufacturing method described in the prior art 3, due to accelerated oxidation through each annealing process for the impurity diffusion to form the bit lines 104 and the formation of the ONO film 102, the sacrificial oxide film 106 above the bit lines 104 may increase its thickness, and large bird's beaks may also grow.
As described above, in manufacturing a semiconductor memory having a buried bit line structure, it is difficult to ensure electrical insulation between the bit lines and the word lines, or even when electrical insulation can be ensured, it may cause bird's beak formation and considerably degrades the charge holding characteristic. These are serious problems.